Methods of enabling polysilicon gate electrodes for high-k gate dielectrics

ABSTRACT

Complementary transistors and methods of forming the complementary transistors on a semiconductor assembly are described. The transistors are formed with an optional interfacial oxide, such as SiO 2  or oxy-nitride, to overlay a semiconductor substrate which will be conductively doped for PMOS and NMOS regions. Then a dielectric possessing a high dielectric constant of least seven or greater (also referred to as a high-k dielectric) is deposited on the interfacial oxide. The high-k dielectric is covered with a thin monolayer of metal oxide (i.e., aluminum oxide, Al 2 O 3 ) that is removed from the NMOS regions, but remains in the PMOS regions. The resulting NMOS transistor diffusion regions contain predominately metal to silicon bonds that create predominately Fermi level pinning near the valence band while the resulting PMOS transistor diffusion regions contain metal to silicon bonds that create predominately Fermi level pinning near the conduction band.

This application is a divisional to U.S. patent application Ser. No.10/913,281, filed Aug. 6, 2004.

FIELD OF THE INVENTION

This invention relates to semiconductor devices and fabricationprocesses thereof. The invention particularly relates to complementarytransistors and a method to fabricate the complementary transistors thatutilize transistor gate dielectric materials possessing a highdielectric constant.

BACKGROUND OF THE INVENTION

Complementary Metal Oxide Semiconductor (CMOS) devices are dominated byn-channel (NMOS) and p-channel (PMOS) transistor structures. Variousphysical characteristics of each type of transistor determine thethreshold voltage (V_(t)) that must be overcome to invert the channelregion and cause a given transistor to conduct majority carriers (eitherby electrons movement in an NMOS device or by hole movement in a PMOSdevice).

One of the controlling physical characteristics is the work function ofthe material used to form the gate electrode of the transistor device.In semiconductor devices, such as a Dynamic Random Access Memory (DRAM)device, the transistor gates are predominantly made of polysilicon andan overlying layer of metal silicide, such as tungsten silicide and thegate dielectric is typically a high quality silicon oxide. The industryhas moved to a transistor gate dielectric possessing a high dielectricconstant of seven or greater (high-k dielectrics) for better leakage atgiven Effective Oxide Thickness (EOT). However, choosing a material withthe appropriate work function as a gate electrode is still a challenge.

Studies have been conducted in one area of using high-k dielectricconcerning Fermi-level pinning at the polysilicon/metal oxide interfaceof the transistor gate structure. Taking HfO₂, for example, the hafniumand the polysilicon form Hafnium-Silicon bonds whose energy level in theband gap causes the Fermi-Level of the polysilicon to be pinned near theconduction band. With this scenario, using the HfO₂ as the transistorgate dielectric in an NMOS device, a small shift in the transistorV_(t), relative to N+ polysilicon on SiO₂ will occur due toHafnium-Silicon interface. However, applying this case in a PMOS device,a large shift in the transistor V_(t) will occur due to theHafnium-Silicon bonds still pinning the Fermi-Level of the polysiliconnear the conduction band.

Taking Al₂O₃, for example, the aluminum and the polysilicon formAluminum-Silicon bonds that cause the Fermi-Level of the polysilicon tobe pinned near the valence band due to the creation of the interfacestates that reside close to the valence band. With this scenario, usingthe Al₂O₃ as the transistor gate dielectric in a PMOS device, a smallshift in the transistor V_(t) will occur due to P+ Aluminum-Siliconinterface. However, applying this case in an NMOS device a large shiftin the transistor V_(t) will occur due to the Aluminum-Silicon interfacestill having the Fermi-Level of the polysilicon being pinned near theconduction band and the transistor will not function in the desiredrange.

CMOS transistor devices that use the traditional polysilicon gateelectrodes in combination with a metal oxide dielectric (high-kdielectric) must be fabricated such that the NMOS and PMOS devices willeach possess a suitable transistor threshold voltage (V_(t)).

There is a need for the construction of CMOS devices using high-kdielectric materials for the transistor gate dielectric which willsuccessfully be used to form both n-channel (NMOS) and p-channel (PMOS)transistors in semiconductor devices.

SUMMARY OF THE INVENTION

Exemplary implementations of the present invention include complementarytransistors and methods of forming the complementary transistors on asemiconductor assembly by optionally forming an interfacial oxide, suchas SiO₂ or oxy-nitride, for electron or hole mobility, to overlay asemiconductor substrate which will be conductively doped for PMOS andNMOS regions. Then a dielectric possessing a high dielectric constant ofleast seven or greater (also referred to herein as a high-k dielectric)is deposited on the interfacial oxide. The high-k dielectric is coveredwith a thin monolayer of metal oxide (i.e., aluminum oxide, Al₂O₃) thatis removed from the NMOS regions, but remains in the PMOS regions. Theresulting NMOS transistor diffusion regions contain predominately metalto silicon bonds that create predominately Fermi level pinning near thevalence band while the resulting PMOS transistor diffusion regionscontain metal to silicon bonds that create predominately Fermi levelpinning near the conduction band.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 is a cross-sectional view of a semiconductor substrate sectionshowing the early stages of an semiconductor assembly having N-WELL andP-WELL regions formed in a silicon substrate partially separated by anisolation material and a thermally grown dielectric layer, which canhaving varying thickness, is formed over the Well regions, according toan embodiment of the present invention.

FIG. 2 is a subsequent cross-sectional view taken from FIG. 1 followingthe formation of a first high-k dielectric layer on the thermally growndielectric layer which in turn is covered with a second high-kdielectric layer.

FIG. 3 is a subsequent cross-sectional view taken from FIG. 2 followingthe patterning of a photoresist over the N-WELL region, thus exposingthe second high-k dielectric layer overlying the P-WELL region.

FIG. 4 is a subsequent cross-sectional view taken from FIG. 3 followingremoval of the exposed second high-k dielectric layer and the strippingof the photoresist.

FIG. 5 is a subsequent cross-sectional view taken from FIG. 4 followingthe deposition of a polysilicon layer and conductive implanting thereof.

FIG. 6 is a subsequent cross-sectional view taken from FIG. 5 followingthe completion of a complementary transistor pair having differingtransistor gate dielectrics.

FIG. 7 is a simplified block diagram of a semiconductor systemcomprising a processor and memory device to which the present inventionmay be applied.

DETAILED DESCRIPTION OF THE INVENTION

The following exemplary implementations are in reference tocomplementary transistors and the formation thereof. While the conceptsof the present invention are conducive to transistor structures forsemiconductor memory devices, the concepts taught herein may be appliedto other semiconductor devices that would likewise benefit from the useof the process disclosed herein. Therefore, the depictions of thepresent invention in reference to transistor structures forsemiconductor memory devices are not meant to so limit the extent towhich one skilled in the art may apply the concepts taught hereinafter.

In the following description, the terms “wafer” and “substrate” are tobe understood as a semiconductor-based material including silicon,silicon-on-insulator (SOI) or silicon-on-sapphire (SOS) technology,doped and undoped semiconductors, epitaxial layers of silicon supportedby a base semiconductor foundation, and other semiconductor structures.Furthermore, when reference is made to a “wafer” or “substrate” in thefollowing description, previous process steps may have been utilized toform regions or junctions in or over the base semiconductor structure orfoundation. In addition, the semiconductor need not be silicon-based,but could be based on silicon-germanium, silicon-on-insulator,silicon-on-saphire, germanium, or gallium arsenide, among others.

An exemplary implementation of the present invention is depicted inFIGS. 1-6. Referring now to FIG. 1, substrate 10 is processed to thepoint where P-WELL region 12 and N-WELL region 13 are formed insubstrate 10. P-WELL region 12 represents a region containing aconcentration of p-type conductive dopants, while N-WELL region 13represents a region containing a concentration of n-type conductivedopants. Isolation material 11 partially separates and electricallyisolates the upper portions of the Well regions from one another.Dielectric material 14 is deposited over the surfaces of N-WELL region12, P-WELL region 13 and isolation material 11. Dielectric material 14may be a thermally grown oxide material or a nitrided thermally grownoxide material formed by methods know to those skilled in the art.Though not shown, a boron barrier layer may also be included if desired.

Referring now to FIG. 2, a first material 20 and second material 21,each being a high-k dielectric material, are deposited on dielectricmaterial 14. The first material 20 may be a metal oxide, preferably HfO₂or HfSiO and the second material 21 may be a metal oxide, preferablyAl₂O₃. The first metal oxide dielectric material 20 must be a materialthat contains a metal component that when allowed to form a metalsilicon interface (such an interface will be formed by a subsequentdeposition of a polysilicon layer as described in reference to FIG. 5),the metal-Silicon bonds will create predominately Fermi level pinningnear the valence band for a subsequently formed NMOS transistor. Thesecond metal oxide dielectric material 21 must be a material thatcontains a metal component that when allowed to form a metal siliconinterface, the metal-Silicon bonds will create predominately Fermi levelpinning near the conduction band in a subsequently formed PMOStransistor. The second metal oxide dielectric material 21 is depositedby a Atomic Layer Deposition (ALD) process know to one skilled in theart. It is preferred that the second metal oxide dielectric material 21,such as Al₂O₃, be deposited only several monolayers in thickness (i.e.,several atomic layers), such that a sufficient amount of aluminum atomscover the surface of the first metal dielectric material in order toprovide the desired Fermi-Level pinning as discussed in the subsequentprocessing steps.

Referring now to FIG. 3, photoresist 30 is formed and patterned to coverthe portion of second metal oxide dielectric material 21 that overliesN-WELL region 13, while exposing the portion of second metal oxidedielectric material 21 that overlies P-WELL region 12.

Referring now to FIG. 4, the exposed portion of the second metal oxidedielectric material is removed and photoresist 30 is stripped, thusleaving behind the portion of second metal oxide dielectric material 21that overlies N-WELL region 13. The remaining portion of second metaloxide dielectric material 21 will provide the necessary metal-siliconbonds required to create predominately Fermi level pinning near theconduction band in a subsequently formed PMOS transistor. For theexposed portion of the first metal oxide dielectric material thenecessary metal-silicon bonds required to create predominately Fermilevel pinning near the valance band in a subsequently formed NMOStransistor.

Referring now to FIG. 5, a silicon material 50, such as a polysiliconlayer, is formed over the exposed portion of first metal oxidedielectric material 20 and the remaining portion of second metaldielectric material 21. The silicon material 50 creates a firstinterface between the first metal oxide dielectric material, containingmetal 1 atoms (overlying the P-WELL region) and a second interfacebetween the second metal oxide dielectric material containing metal 2atoms (overlying the N-WELL region). During deposition of the siliconmaterial, metal 1 to silicon bonds will form along the first interface.In the same manner metal 2 to silicon bonds will form along the secondinterface. In one example, if first metal oxide dielectric material isHfO₂ or HfSiO, hafnium to silicon bonds will be formed. If the secondmetal oxide dielectric material is Al₂O₃, then aluminum-silicon bondswill be formed.

Referring now to FIG. 6, process steps known to one skilled in the artare conducted to form a pair of completed CMOS transistors, namely NMOStransistor 67 and PMOS transistor 68, separated by trench isolationmaterial 11. The transistors are formed using conventional fabricationtechniques to pattern and etch each transistor gate, followed byimplanting the source and drain regions 64 into P-WELL 12 to an n-typeconductivity to form an n-channel transistor (NMOS) 67 and implantingthe source and drain regions 65 into N-WELL 13 to a p-type conductivityto form a p-channel transistor (PMOS) 68. The transistor gate structureof NMOS transistor 67 is electrically isolated from P-WELL 12 by gatedielectric 60 which is made up of thermally grown oxide 14 and a firstmetal oxide dielectric material 20, such as HfO₂. The transistor gatestructure is made up of silicon material 50, such as polysilicon and ametal silicide 62, such as tungsten silicide. The gate structure is thencovered with isolation gate spacers 66 and isolation cap 63. Siliconmaterial 50 and first metal oxide dielectric material form a metaldielectric/silicon interface and thus metal-silicon bonds in the NMOStransistor gate structure that create predominately Fermi level pinningnear the valance band as described in the present invention. In theexample using HfO₂ or HfSiO as the first metal oxide dielectricmaterial, the hafnium atoms and the silicon atoms form hafnium-siliconbonds that create predominately Fermi level pinning near the valanceband.

The transistor gate structure of PMOS transistor 68 is isolated fromN-WELL 13 by gate dielectric 61, which is made up of thermally grownoxide 14, a first metal dielectric material 20, such as HfO₂, and asecond metal oxide dielectric material 21, such as Al₂O₃. The transistorgate structure is made up of silicon material 50, such as polysiliconand a metal silicide 62, such as tungsten silicide. The gate structureis then covered with isolation gate spacers 66 and isolation cap 63.Silicon material 50 and second metal oxide dielectric material form ametal dielectric/silicon interface and thus metal-silicon bonds in thePMOS transistor gate structure that create predominately Fermi levelpinning near the conduction band as described in the present invention.In the example using Al₂O₃ as the second metal oxide dielectricmaterial, the aluminum atoms and the silicon atoms form aluminum-siliconbonds that create predominately Fermi level pinning near the conductionband.

The exemplary embodiment has been discussed in reference to forming acomplementary transistor pair for use in CMOS applications, such asmemory devices. However, these concepts, taught in the exemplaryembodiments, may be utilized by one of ordinary skill in the art to formcomplementary transistor pairs for use in most all CMOS applications.For example, the present invention may be applied to a semiconductorsystem, such as the one depicted in FIG. 7, the general operation ofwhich is known to one skilled in the art.

FIG. 7 represents a general block diagram of a semiconductor systemcomprising a processor 70 and a memory device 71 showing the basicsections of a memory integrated circuit, such as row and column addressbuffers, 73 and 74, row and column decoders, 75 and 76, sense amplifiers77, memory array 78 and data input/output 79, which are manipulated bycontrol/timing signals from the processor through control 72.

It is to be understood that, although the present invention has beendescribed with reference to two exemplary embodiments, variousmodifications, known to those skilled in the art, may be made to thedisclosed structure and process herein without departing from theinvention as recited in the several claims appended hereto.

1. A complementary transistor pair on a semiconductor assemblycomprising: an NMOS transistor comprising first metal-silicon bonds thatcreate predominately Fermi level pinning near the valance band; and aPMOS transistor comprising second metal-silicon bonds that createpredominately Fermi level pinning near the conductive band.
 2. Thecomplementary transistor pair of claim 1, wherein the firstmetal-silicon bonds comprise hafnium-silicon bonds.
 3. The complementarytransistor pair of claim 1, wherein the second metal-silicon bondscomprise aluminum-silicon bonds.
 4. A complementary transistor pair on asemiconductor assembly comprising: an NMOS transistor comprisinghafnium-silicon bonds that create predominately Fermi level pinning nearthe valance band; and a PMOS transistor comprising aluminum-siliconbonds that create predominately Fermi level pinning near the conductiveband.
 5. A semiconductor memory device having a complementary transistorpair comprising: an NMOS transistor comprising first metal-silicon bondsthat create predominately Fermi level pinning near the valance band; anda PMOS transistor comprising second metal-silicon bonds that createpredominately Fermi level pinning near the conductive band.
 6. Thecomplementary transistor pair of claim 5, wherein the firstmetal-silicon bonds comprise hafnium-silicon bonds.
 7. The complementarytransistor pair of claim 5, wherein the second metal-silicon bondscomprise aluminum-silicon bonds.
 8. A semiconductor memory device havinga complementary transistor pair comprising: an NMOS transistorcomprising hafnium-silicon bonds that create predominately Fermi levelpinning near the valance band; and a PMOS transistor comprisingaluminum-silicon bonds that create predominately Fermi level pinningnear the conductive band.
 9. A complementary transistor pair on asemiconductor assembly comprising: a PMOS transistor comprising: a PMOStransistor gate dielectric of silicon dioxide, a hafnium containingoxide and an aluminum oxide; and a PMOS transistor gate comprising asilicon material directly overlying the aluminum oxide, the siliconmaterial and the aluminum oxide forming aluminum-silicon bonds thatcreate predominately Fermi level pinning near the valance band; and anNMOS transistor comprising: an NMOS transistor gate dielectric of thesilicon dioxide and the hafnium containing oxide; and an NMOS transistorgate comprising the silicon material directly overlying the hafniumcontaining oxide, the silicon material and the hafnium containing oxideforming hafnium-silicon bonds that create predominately Fermi levelpinning near the conductive band.
 10. The complementary transistor pairof claim 9, wherein the hafnium containing oxide is HfO₂.
 11. Thecomplementary transistor pair of claim 9, wherein the hafnium containingoxide is HfSiO.
 12. The complementary transistor pair of claim 9,wherein the silicon material is polysilicon.
 13. The complementarytransistor pair of claim 9, wherein the silicon dioxide is a nitridedsilicon dioxide.
 14. A semiconductor memory device having acomplementary transistor pair comprising: a PMOS transistor comprising:a PMOS transistor gate dielectric of silicon dioxide, a hafniumcontaining oxide and an aluminum oxide; and a PMOS transistor gatecomprising a silicon material directly overlying the aluminum oxide, thesilicon material and the aluminum oxide forming aluminum-silicon bondsthat create predominately Fermi level pinning near the valance band; andan NMOS transistor comprising: an NMOS transistor gate dielectric of thesilicon dioxide and the hafnium containing oxide; and an NMOS transistorgate comprising the silicon material directly overlying the hafniumcontaining oxide, the silicon material and the hafnium containing oxideforming hafnium-silicon bonds that create predominately Fermi levelpinning near the conductive band.
 15. The complementary transistor pairof claim 14, wherein the hafnium containing oxide is HfO₂.
 16. Thecomplementary transistor pair of claim 14, wherein the hafniumcontaining oxide is HfSiO.
 17. The complementary transistor pair ofclaim 14, wherein the silicon material is polysilicon.
 18. Thecomplementary transistor pair of claim 14, wherein the silicon dioxideis a nitrided silicon dioxide.